This disclosure relates to integrated circuit devices. More specifically, to designing interconnect wiring structures in semiconductor devices.
Integrated circuits are fashioned by creating a plurality of devices in a substrate which are interconnected by multiple layers of interconnections. The process starts with a chip designer constructing the layout of a new chip design with the use of an electronic design automation (EDA) system. One of the tasks automated by such tools is the wire routing, or simply routing, of the wiring or nets between devices on the integrated circuit layout within the available space allocated to the metal layers and the vias which interconnect the metal layers. Speed in the design process is an important criterion for an EDA system. Design tools which provide rapid, accurate results, especially for large complex designs are valuable so that designers can make decisions quickly on design tradeoffs without needing to wait for days to even weeks to obtain accurate results from the system.
Global routing in modern circuit design is used to establish an approximate route of the wiring between devices. Detail routing follows the global routing and determines the precise paths for the nets. The global routing is simpler than the detail routing problem, because it does not see many of the small details that detail routing has to solve. Therefore, it has several advantages including that global routing is much faster than detail routing. Further, global routing can be designed in such a way that its results are “provably optimal”, in other words, it has some quality guarantees. Global routing is used as guidance for detail routing, e.g., used for wire resource allocation and fast estimation purposes.
In detail routing, the router embeds wires onto the chip area according to the global routing guidance. Only if a feasible solution cannot be found, a rip-up and reroute approach is taken to make up space in order to close the open connection. It is desirable that the global routing be as accurate as possible to minimize computations needed in the rip-up and reroute step. One of the reasons for additional detail routing once the initial chip design is complete is an engineering change order (ECO). Engineering change orders are common when the designers are evaluating design trade-offs. Unfortunately, current global routing models are weak in anticipating the problems caused by subsequent ECO detail routing. By its nature, the global routing is coarse and does not see the details involved in an engineering change order. This leads to an undesirably high amount of rip-up and reroute in the detail ECO routing which causes a high runtime cost. Furthermore, during global routing, there is a poor selection of bystanders. A “bystander” is a wiring net which is selected for rip-up to accommodate the global wire route.
The present disclosure presents an advanced electronic design mechanism to alleviate these problems.